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path: root/src/gpgpu-sim/shader.h
AgeCommit message (Expand)Author
2014-08-14Cleaning up interconnection network memory partition to core statistics. Now ...Tayler Hetherington
2014-08-14Cleaning up the interconnection core to memory partition statisticsTayler Hetherington
2014-08-14Fixed at least one error in the valgrind build. Forgot to initial a member va...Tim Rogers
2014-08-14MergingTim Rogers
2014-08-14MergingTim Rogers
2014-08-14Making this const correctTim Rogers
2014-08-14Adding an accessor to the distro vectorTim Rogers
2014-08-14Adding in a statistic for number of dynamic warps issued by their ID.Tim Rogers
2014-08-14Adding in a dynamic warp_id fieldTim Rogers
2014-08-14cleanig inc_stat functions + remove unused L2D_config parameter was mistakenl...Ahmed El-Shafiey
2014-08-14cleaning the duty_cycle_stats collection code in the writeback stageAhmed El-Shafiey
2014-08-14Merging Power model into FermiTayler Hetherington
2014-08-14Revision #2 of modifying the cache hierarchy.Tayler Hetherington
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code replication,...Tayler Hetherington
2014-08-14Fixing compile error on my machineAndrew M. B. Boktor
2014-08-14Fixing an error reported by valgrind.Tim Rogers
2014-08-14Fix for bug 9: Now querying the state of the pdom stack in call_imp and callp...Ayub Gubran
2014-08-14Adding a two level scheduler as described in the ISCA 2012 tutorialAndrew M. B. Boktor
2014-08-14Removing some bottlenecks that limit that peak-IPCAndrew M. B. Boktor
2014-08-14Adding configurable instruction latencies and initiation intervalsAndrew M. B. Boktor
2014-08-14This changelist adds the following:Andrew M. B. Boktor
2014-08-14-Bug 146 fix (Adding perfect memory interface)Ahmed El-Shafiey
2014-08-14Changed arch_rech type to store 16 registers, 8 input and 8 output. 8 inputs ...Inderpreet Singh
2014-08-14Adding a check for copmliance between the runtime simulation config and MAX_T...Wilson Fung
2014-08-14Changes needed for the new fermi configs to work.Andrew M. B. Boktor
2014-08-14Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify the...Wilson Fung
2014-08-14Grouped all instruction counting code into a common member function in shader...Wilson Fung
2014-08-14Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more detai...Wilson Fung
2014-08-14Integrating the pure functional simulationAyub Gubran
2014-08-14Fixing the atomics I broke with the insn count fixTim Rogers
2014-08-14Fixing the varying instruction count when the cache configuration changes.Tim Rogers
2014-08-14Integration change. CL 8980 - l1 cache stat printTim Rogers
2014-08-14Fix for Bug 110 - integrates in CL 10258 from tm-test branchInderpreet Singh
2014-08-14change copyright notice to include authorsTor Aamodt
2011-06-29changing copyright to BSDTor Aamodt
2011-05-25Fix bug #100: local memory address translation returns multiple addressesInderpreet Singh
2011-03-03refactor pipeline stage namesTor Aamodt
2011-02-01Added configurable schedulers!aturner
2011-01-24Adds highly configurable opperand collectoraturner
2011-01-20Integration change. Bug fixes from AMD-CMU trace gen branch. Wilson Fung
2010-12-28- parameter memory and active threads now part of kernel_info_t:Tor Aamodt
2010-12-28- Checkpointing new support for concurrent kernel execution (CUDA only, not O...Tor Aamodt
2010-11-30integrate changes (makes code more modular, i would argue)Tor Aamodt
2010-11-29make an explicit read operands stageTor Aamodt
2010-11-29integrate mask changesTor Aamodt
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
2010-11-28adding 1st level data cacheTor Aamodt
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
2010-10-241. updates to .gdbinit fileTor Aamodt
2010-10-24add back per shader icount tracking for visualizerTor Aamodt
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