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counting the number of flits arriving at the cores instead of the number of flits leaving each memory partition.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15746]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15745]
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variable.
I thought the init() function where dynamic_warp_id is initialized was called on construction.
It is not. Added a default value in the constructor. Maybe a code review would have caught this :)
Also cleaned up some weird code I had in the ptx_instruction::to_string().
Also trimmed out tabs from our stored source line string so it is much more readable on print
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15310]
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//depot/gpgpu_sim_research/fermi_tim/...
to //depot/gpgpu_sim_research/fermi/...
Integrating CLs up to 15295. Descriptions of these CL's are included.
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A couple changes to aeriel-vision for warp issue plot support
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More arielvision changes to support the variable-entry length stacked bar chart
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Properly printing the right resolution of dynamic warp ids
***.
Generalized the scheduler code and added detailed statistics for which warps issue each cycle.
Verified the execution of the LRR scheduler - still have to get the two level scheduler to work.
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Implementing the 2lvl scehduler has it has been originally coded.
LRR on both the inner and outer levels
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Adding in a debug tracing system to GPGPU-Sim.
I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin.
This also allows for print streams so the user can decided which traces they would like to see.
Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building.
Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need.
This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big.
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Allowing the trace to be specified in the Make.
Run Make TRACE=0 to compile the code without any traces
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Allowing prints from the performance sim to get the actual ptx instruction text
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Getting the two level scheduler to actaully work...
What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper.
Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken.
Maybe if the original author had access to the tracing functions this would not have happened.
The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used.
For example if this instruction was creating a long op:
ld r6 [r1]
It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6.
Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared....
The only way anyone ever thought this worked is if they did not test it....
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Reworking the warp schedulers to share common code.
Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR.
Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some
additional criteria or information printed.
Verified that the schedulers all work to a first order based on traces.
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Making it so you can run the stats collection scripts from any directory.
Also allow the caller to specify a stats file instead of just assume its always the same one
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
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//depot/gpgpu_sim_research/fermi_locality/...
to //depot/gpgpu_sim_research/fermi/...
Adding in some protected constructors to the core cache classes.
This allows us to customize caches (for example having them use a custom tag array) more easily.
Also I made the in-class tag_array object in the baseline_cache into a pointer. This allows derived classes to easily create custom tag arrays.
I think in general, class extendibility is increased when pointers are used instead of in-object storage.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15223]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15211]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15209]
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Also fixing some really scary code that was memsetting the "*this" to 0.
The code sort of worked since there was only one member on the derived class (that was never referenced) and it
had no virtual functions. What I did to fix this is equally ugly, but far less dangerous.
I get a pointer to the start of the "plain old data (pod)" section of the class then memset it to 0.
Now the derived stats class can have more stuff on it than pod and we don't have to worry about stomping.
The "right" fix here is to not derive from pod and just make it a member with an accessor.
However, this is going to require all the client code to be re-written.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15203]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15198]
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mistakenly defined in shader class and removing wrong increment for store instructions
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15121]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14828]
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//depot/gpgpu_sim_research/fermi_power/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
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Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations.
Added WRITE_EVICT cache write policy.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
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replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only".
Still need to implement Ahmed's sectored cache implementation.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13703]
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Is really harmless since you can call delete on primatives allocated with new[] without consequence (all delete [] does is ensure that the destructors will be called)
Still, it is always good practice to de-allocate anything allocated with new[] with delete[] - just in case the type allocated changes and the person that changes it forgets to update the de-allocation.
Really, this little array should be on the stack...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13414]
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callp_imp using a core_t function, thus moving the querying function into the abstract model of the core instead of shader_core_ctx which represents the performance mode. This code simplify the querying and also avoid the unnecessary calling hierarchy that was used.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13375]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13261]
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- FUs depended on the result bus to know if they are going to be used on a certain cycle, this is not the case anymore, occupied bitvectors are added
- A configurable number of result buses is added (the number of buses is equal to the EX_WB pipe width)
- Modified the Fermi config file to add two ports to the operand collector
IPC with a theoretical limit of number_of_SMs*64 is achievable using this configuration
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12349]
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The observed latencies are reduced by 5 to account for other stages in the SM pipeline
Eventually this should be calibrated against the microbenchmarks
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12310]
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1. A configurable number of functional units within each SM
2. A configurable pipeline widths (i.e. Issue width, writeback width ...).
Merging
//depot/gpgpu_sim_research/fermi_replay/distribution/src/...
to //depot/gpgpu_sim_research/fermi/distribution/src/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12091]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11877]
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because one can have 4 input operands and 4 register operands in a surface store instruction.
Fixed arch_regs for memory instructions being ignored in the pre-decode statge.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11576]
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MAX_THREAD_PER_SM. Also decreased LOCAL_MEM_SIZE_MAX to 8kB to make it fit within our allotted memory space (otherwise the simulator may mistaken global memory access as local memory accesses).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11520]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11511]
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the order in which cores are simulator per cycle. Also adding support for calling function with empty parameter list.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11489]
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shader_core_ctx. Now m_num_sim_insn counts scalar thread instructions. A new counter is added for warp instructions.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11472]
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detail. For verification, I added a directed test with a pre-calculated number of shared memory instructions.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11454]
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Merging
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.cc
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/gpu-sim.h
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.cc
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/gpgpu-sim/shader.h
to //depot/gpgpu_sim_research/fermi/distribution/src/gpgpu-sim/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11287]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10754]
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The problem was 2-fold:
1) If all the lanes hit, we were not incrementing the instruction count since the instruction did not progress to the WB stage, the scoreboard relasing is done in the ldst_unit::cycle function for cache hits. Added code there to increment the instrcution count.
2) Loads were some lanes hit in cache and some lanes do not were not being comepletely counted. Only the lanes sent off to the memory system were being counted because we were setting the warp's active lanes to the access's acrtive lanes.... I am not sure why this code was there...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10737]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10726]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10299]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
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Fix bug #101: Coalescing allows multiple accesses per thread for local memory access
This will break atomics which assume at most one thread per mem_fetch. It did not break scoreboard as that logic tracks mem_fetches at warp level, not thread level.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9303]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8544]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8472]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8407]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8389]
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Parameters are finalized at kernel launch, which means the contents
of parameter memory are initialized. Kernel arguement names have a
fixed order, hence same address should be assigned on subsequent
kernel launches of same kernel in other streams provided the data size
param_t::size of arguments for each kernel launch is identical (an
assertion has been added to check this is true).
- passing regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8303]
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OpenCL)
This changelist adds full support for streams supported by a new class,
stream_manager and enables concurrent execution of kernels from different
streams.
- fast_regression.sh fails for simpleMultiCopy, simpleStreams (other tests
passing)
** Known issues **
- Kernel parameter passing is not done correctly for concurrent kernel execution
(somehow concurrentKernels is not affected by this): the parameters are
stored inside function_info, which is shared among parallel kernel launches
so that the values passed into the launch are likely to get overwritten if
multiple grids are launched in parallel streams.
- Statistics are printed out whenever the simulation thread runs out of
cuda commands (doesn't make sense to print out when a kernel ends during
concurrent kernel execution). This will probably require further tweaking
so as to be more compatible with data collection scripts.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8302]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8179]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8174]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8170]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8153]
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stalling to send four requests per warp into L1T tag lookup.
If L1T is really 32B blocks (as per Henry's paper), this suggests
banking of L1T needs to be modeled.
Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
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2. update texture to bypass ROP-delay queue... correlation now 0.9592
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7912]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7910]
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