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path: root/src/gpgpu-sim/gpu-sim.cc
AgeCommit message (Expand)Author
2014-08-14MergingAhmed El-Shafiey
2014-08-14fixing a segfault problem for Quadro config with interconnect statsAhmed El-Shafiey
2014-08-14setting power model congfig to zero by default (because the mcpat.xml is avai...Ahmed El-Shafiey
2014-08-14Merging Power model into FermiTayler Hetherington
2014-08-14Fixed the shared memory bank conflict model for GTX 480 and Tesla C2050. Now...Wilson Fung
2014-08-14- Fixing cache configuration groupings -> Now <cache configs>, <cache policie...Tayler Hetherington
2014-08-14Fixing the round-robin block distribution among SIMT core clusters in gpgpu_s...Wilson Fung
2014-08-14Adding a two level scheduler as described in the ISCA 2012 tutorialAndrew M. B. Boktor
2014-08-14Fixed GDDR5 parameters in Fermi config:Wilson Fung
2014-08-14Fix for bug 168 (internal). The overall average memory latency should now be...Wilson Fung
2014-08-14Fixing typoAndrew M. B. Boktor
2014-08-14A much easier way to attempt to fix the problem targeted by CL12362 is to jus...Andrew M. B. Boktor
2014-08-14Integrated in CL12342 from coherence branch; fix for bug #160Inderpreet Singh
2014-08-14This changelist adds the following:Andrew M. B. Boktor
2014-08-14Changing the configs to be backward compatible by disabling bank groups by de...Andrew M. B. Boktor
2014-08-14This changelist implements the following:Andrew M. B. Boktor
2014-08-14Changing the defaults for ROP and DRAM latency to match Quadro config as befo...Wilson Fung
2014-08-14Turned ROP and DRAM latency/delays into optionsInderpreet Singh
2014-08-14Adding option 'gpgpu_simt_core_sim_order' which allow the user to specify the...Wilson Fung
2014-08-14Fixed the stat collection for gpgpu_n_shmem_insn. See Bug 128 for more detai...Wilson Fung
2014-08-14Fixing bug 126. Now DXTC runs to completion by not giving correct result (ex...Wilson Fung
2014-08-14Revived PC-Histogram in AerialVision.Wilson Fung
2014-08-14Integrating the pure functional simulationAyub Gubran
2014-08-14Fix for Bug 117 - Cannot disable L2 caches.Inderpreet Singh
2014-08-14Printing out the simulation rateTim Rogers
2014-08-14Making the default L2 something saneTim Rogers
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like the...Ali Bakhoda
2014-08-14Integration change. - CL 9058 , adding the l1 cache stat print to the end of ...Tim Rogers
2014-08-14Ejection from the interface buffer between interconnet and L2 happens in L2 c...Ali Bakhoda
2014-08-14Fix for Bug 110 - integrates in CL 10258 from tm-test branchInderpreet Singh
2014-08-14Fixed the DRAM timing model to add the write-read turn and write-precharge de...Wilson Fung
2014-08-14change copyright notice to include authorsTor Aamodt
2011-06-29changing copyright to BSDTor Aamodt
2011-02-01Added configurable schedulers!aturner
2011-01-24Adds highly configurable opperand collectoraturner
2011-01-20Integration change. Bug fixes from AMD-CMU trace gen branch. Wilson Fung
2010-12-28- parameter memory and active threads now part of kernel_info_t:Tor Aamodt
2010-12-28- Checkpointing new support for concurrent kernel execution (CUDA only, not O...Tor Aamodt
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
2010-11-28adding 1st level data cacheTor Aamodt
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
2010-10-241. updates to .gdbinit fileTor Aamodt
2010-10-24add back per shader icount tracking for visualizerTor Aamodt
2010-10-241. adding top level configuration class and making shader and memory configur...Tor Aamodt
2010-10-211. rewriting memory access generation code (from scratch), why not...Tor Aamodt
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
2010-10-18Re-designed cache model:Tor Aamodt
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
2010-10-161. refactoring histogram/logger so that classes are in header filesTor Aamodt
2010-10-161. moving address decoding into a class (and out of cache entirely)Tor Aamodt
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